1. Field of the Invention
The present invention generally relates to a row redundancy circuit, and more specifically, to a row redundancy circuit wherein a redundant main wordline corresponds to eight or more redundant sub wordlines to reduce the number of redundant main wordlines and a repair method using the row redundancy circuit.
2. Description of the Background Art
In general, a semiconductor memory having only one defect in one of numerous microscopic cells is considered defective, which results in reduction of yield.
A redundancy circuit, which has been provided to improve the yield, replaces failed cells with normal memory cells prepared in a memory.
That is, the redundancy circuit repairs defective memory cells by replacing wordlines connected defective cells with redundancy wordlines. Specifically, if a row address for selecting defective cells is designated, a conventional row redundancy circuit performs a row redundancy operation by enabling wordlines connected to repaired cells instead of the defective cells.
In the conventional row redundancy circuit, one redundant main wordline corresponds to four redundant sub-wordlines. One of the four redundant sub-wordlines is enabled in response to a signal obtained by predecoding lower 2 bits of the row address for the redundancy operation.
FIG. 1 is a circuit diagram of a conventional row redundancy circuit.
If an address of a defective cell is applied to the row redundancy circuit of FIG. 1, the row redundancy circuit performs a logic operation on output signals rwe0<0>˜rwe0<7> and rwe1<0>˜rwe1<7> of a fuse box array (not shown) for replacing an address path which selects the defective cell with a path which selects the repaired cell. Then, the row redundancy circuit outputs a control signal rwe_sum for generating control signals rwez0 and rwez1 to enable a repair cell array block and a boosting signal to drive a sub-wordline of the enabled cell array block.
The row redundancy circuit comprises NOR gates NOR1˜NOR4, NAND gates ND1˜ND3, and inverters IV1 and IV2. The NOR gates NOR1˜NOR4 perform a NOR operation on output signals rwe0<0>˜rwe0<3>, rwe0<4>˜rwe0<7>, rwe1<0>˜rwe1<3> and rwe1<4>˜rwe1<7> from four adjacent fuse boxes. The NAND gate ND1 performs a NAND operation on output signals from the NOR gates NOR1 and NOR2, and the NAND gate ND2 performs a NAND operation on output signals from the NOR gates NOR3 and NOR4. The inverters IV1 and IV2 invert output signals from the NAND gates ND1 and ND2 to output control signals rwez0 and rwez1, respectively. The NAND gate ND3 performs a NAND operation on output signals from the inverters IV1 and IV2 to output a control signal rwe_sum.
In the conventional row redundancy circuit, each fuse box (not shown) corresponds one by one to a redundant main wordline (not shown) which corresponds to four redundant sub-wordlines (not shown). The conventional row redundancy circuit controls generation of a boosting signal in response to a predecoding signal of lower bits of a repaired row address, thereby selecting one of the four redundant sub-wordlines.
In the conventional row redundancy circuit, the redundant main wordline comprises a metal layer in a core region, and a metal line is assigned every four sub-wordlines. As a result, it is difficult to arrange a power line between main wordlines due to insufficient space.